Fontem paginae Porta ET inspicere

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|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INDUCTA''' || '''EDUCTUM'''
|- bgcolor="#ddeeff" align="center"
| A || B || A ET B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 1
|}
'''Porta ET''' seu Anglice '''porta AND''' est [[porta logica]] digitalis quae [[Coniunctio logicalis|coniunctionem logicalem]] efficit. Gerit ut [[tabula veritatis]] quae ad dextram videre potest. Datum eductum est SUPERNUM (1) solum si uterque data inducta portae sunt SUPERNA. Si nullum aut solum unum datum inductum portae est SUPERNUM, data eductum est SUBMISSUM (0). In sensu alio, functio ET ''minimum'' duorum digitorum educit, sicut [[Porta VEL|functio VEL]] ''maximum'' educit.

==Symbola==
Sunt tria symbola pro portis ET: symbolum [[ANSI]] ("Americanum" aut "militare"), symbolum [[IEC]] ("Europaeum" aut "rectangulare") aut [[IEEE]], et obsoletum symbolum [[DIN]]. Lex IEEE et symbola "formarum distinctarum" et "formarum rectangularum" pro portis logicis simplicis sinit. Si vis, vide etiam [[Porta logica#Symboli|Symboli Portae Logicae]].

<gallery>
Fasciculus:AND ANSI Labelled.svg|Symbolum MIL/ANSI <ref>{{cite book|url=http://books.google.com/books?id=74amDes2TE8C&pg=PA59&lpg=PA59&dq=mil+logic+gate+symbols&source=bl&ots=k8crBOmev5&sig=zwzDQrqq86ZfzSVLhqdEJ1dbpWs&hl=en&ei=fTnbTMzuI8uUnAfy3cEW&sa=X&oi=book_result&ct=result&resnum=5&ved=0CCkQ6AEwBA#v=onepage&q=mil%20logic%20gate%20symbols&f=false|title=Aircraft Electrical and Electronic Systems|author=Michael H. Tooley, Mike Tooley, David Wyatt|page=59|publisher=Butterworth-Heinemann|language=Anglice|year=2008}}</ref>
Fasciculus:AND IEC.svg|Symbolum IEC/IEEE <ref>{{cite book|url=http://www.ddpp.com/DDPP3_pdf/IEEEsyms.pdf|title=Digital Design Principles and Practices|author=John F. Wakerly|edition=4a|year=2005|isbn=0-13-186389-4|publisher=Prentice Hall}}</ref>
Fasciculus:AND DIN.svg|Symbolum DIN
</gallery>

==Aequatio Booleana==
Porta ET cum inducta A et B, et eductum C hunc aequationem logicam efficit:

{| align=center style="text-align:center"
|<math>C = A \cdot B</math>
|}

==Forma==
<gallery>
Fasciculus:NMOS AND gate.png|Porta ET, [[NMOS]] facta.
</gallery>

===Forma alterna===
Si portae ET propriae non adsunt, porta ET ex portis [[Logica NON-ET|NON-ET]] aut [[Logica NON-VEL|NON-VEL]] creare potest, quia illae portae sunt ''portae universales'',<ref>{{cite book
|author=M. Morris Mano et Charles R. Kime|title=Logic and Computer Design Fundamentals|edition=3a|publisher=Prentice Hall|year=2004|page=73.}}</ref> quod portas NON-ET aut NON-VEL creare portas omnes alias posse significat. Quamquam portae AUT portas alias creare possunt, est rarum.

==Notae==
<references/>

{{NexInt}}
* [[Algebra booleana (logica)]]
* [[Logica NON-VEL]]
* [[Logica NON-ET]]
* [[Porta VEL]]
* [[Porta logica]]
* [[Porta NON]]
* [[Porta NON-VEL]]
* [[Porta NON-ET]]
* [[Porta AUT]]

[[Categoria:Portae Logicae]]